The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A FET includes a gate electrode structure as a control electrode and spaced apart source and drain electrodes (i.e., source and drain regions) between which a current can flow. A control voltage applied to the gate electrode structure controls the flow of current through a channel region between the source and drain electrodes.
The gain of an FET, usually defined by the transconductance (gm), is proportional to the mobility of the majority carrier in the transistor channel region. The current carrying capability of an MOS transistor is proportional to the transconductance times the width of the channel region divided by the length of the channel (gmW/l). FETs are usually fabricated on silicon substrates with a (100) crystallographic surface orientation, which is conventional for silicon technology. For this and many other orientations, the mobility of holes, the majority carrier in a P-channel FET (PFET), can be increased by applying a compressive longitudinal stress to the channel region. A compressive longitudinal stress can be applied to the channel region of a FET by embedding an expanding material such as pseudomorphic silicon germanium (SiGe) formed by a selective epitaxial growth process in the silicon substrate at the ends of the transistor channel region (epitaxial SiGe at the ends of the transistor channel also referred to herein as “eSiGe strain-inducing fill”). The eSiGe strain-inducing fill is doped with an appropriate P-type dopant such as boron (B) to form the source and drain regions of the PFET.
As device sizes decrease, such as to 28 nm critical dimensions (CD) devices and below, higher optical resolution lithography techniques are used for forming, for example, extension and halo implants in the IC after formation of the source and drain regions. One such high resolution technique is argon fluoride (ArF) laser lithography, which uses an ArF photoresist for selectively implanting various layers of the IC. ArF photoresists typically cannot be removed with standard O2-based plasma strips but rather are removed using more aggressive NH3/O2-based plasma strips. Unfortunately, it has been found that by exposing a boron doped eSiGe strain-inducing fill to the NH3/O2-based plasma strips and heating the IC during plasma stripping and/or during subsequent processing, localized delamination of the boron doped eSiGe strain-inducing fill can result. In particular, hydrogen produced from the NH3/O2-based plasma strips diffuses into the boron doped eSiGe strain-inducing fill. During heating of the IC (e.g., during plasma stripping and/or further downstream processing), the diffused hydrogen accumulates or agglomerates and can form bubbles or blisters that result in localized delamination of the boron doped eSiGe strain-inducing fill.
Accordingly, it is desirable to provide integrated circuits including a boron doped eSiGe strain-inducing fill with improved robustness for processing and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.